Wireless systems are becoming a fundamental mode of telecommunication in modern society. In order for wireless systems to continue to penetrate into the telecommunications market, the cost of providing the service must continue to decrease and the convenience of using the service should continue to increase. In response to increasing market demand, radio standards around the world have been proliferated based upon digital modulation schemes. Consequently, it is often advantageous to have a receiver that is capable of communication using more than one of these standardized techniques. In order to do so, it is necessary to have a receiver that is capable of receiving signals that have been modulated according to several different modulation techniques.
Existing receivers are implemented using double conversion (or heterodyne) receiver architectures. A double conversion receiver architecture is characterized in that a received radio-frequency (RF) signal is converted to an intermediate frequency (IF) signal, which is subsequently converted to baseband. In addition, gain control is also typically applied at the IF. However, double conversion receivers have the disadvantage of utilizing a great number of analog circuit components, thus, increasing the cost, size, and power consumption of the receiver.
A direct conversion receiver, also sometimes called a zero-IF receiver, provides an alternative to the traditional double down conversion architecture. This is particularly attractive for the use in wireless systems, especially in handsets, since direct conversion receivers lend themselves more easily to monolithic integration than heterodyne architectures. Also, direct conversion exhibits immunity to the problem of image since there is no IF.
However, there exist design issues associated with the direct conversion architecture. The most serious problem is a direct current (DC) offset in the baseband, which appears in the middle of the down-converted signal spectrum, and may be larger than the signal itself. This phenomenon is caused by local oscillator leakage and self-mixing. Furthermore, mismatch between the in-phase (I) component and the quadrature (Q) component, occurring in the quadrature down-conversion, can lead to corrupted signal constellation, thereby increasing the number of bits in error, due to the differences which may occur in the I and Q signal amplitudes and phases.
Advancement in semiconductor process technologies allows usage of oversampling bandpass delta-sigma analog-to-digital conversion in the RF frequencies, which is a new promising low-cost and reliable technique to digitize RF signals. The delta-sigma converter comprises a bandpass filter, which consists of a series of resonators in cascade, an analog-to-digital converter (A/D), that generates the converted digital output signal, and a digital-to-analog converter (D/A) that produces a plurality of analog signals converted from the digital output signal to be feed back to the resonator inputs. The first error signal is produced by the difference between the input RF signal and the first feedback signal from the D/A. A first resonator in the filter stage amplifies the first error signal to produce a more refined error signal, which is subtracted from a second feedback signal from the D/A. The sequence is repeated down the resonator stages. The output error signal from the last resonator in the bandpass filter is then sampled by the A/D. The digitized signal is converted to a feedback signal via the D/A. In order to achieve feedback stability, the sampling frequency of the A/D must be at least four times the RF signal frequency, and the digital output reproduces the high-frequency waveform of the input RF signal.
Nevertheless, oversampling an RF signal is not quite practical given the current advancement in process technologies, where the sampling clock rate may exceed tens of gigahertz. The inherent clock jitter in the sampling clock to the A/D, due to thermal agitation at the molecule level that generates phase noise in clock oscillators, severely limits the analog-to-digital conversion resolution. Also, pre-processing of the digitized RF signal requires an impractically high clock rate in the tens of gigahertz range.